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ENEX 302Bachelor in Electronics, Communication and Information Engineering · Semester 51 Paper Available

Embedded Systems

Past examination question papers and complete curriculum syllabus for Embedded Systems (ENEX 302), Bachelor in Electronics, Communication and Information Engineering Semester 5 under Institute of Engineering (IOE), Tribhuvan University.

Sem 5 Subjects (6)View Full Semester Overview →
ENSH 304Probability and StatisticsENCT 305Artificial IntelligenceENEX 301Filter DesignENEX 302Embedded SystemsENEX 303Propogation and AntennnaENEX 325-344Elective I
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5th-sem_Embedded Systems.pdf

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Most Frequently Asked Questions

Top recurring IOE board exam questions for Embedded Systems with verified mark schemes, formula notation, and recurrence frequency.

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Year-wise & Session-wise Exam Papers

Complete questions from each exam session (Regular & Back exams from 2082 to 2069) for Embedded Systems. Click any session paper to expand.

Showing 7 questions across 1 exam session papers
Institute of Engineering • 2082 Chaitra Board Examination
Q1[2 Marks]Introduction
Define embedded system with its key characteristics. Differentiate between a simulator and an emulator in an embedded system development.
Q2[4 Marks]Core of Embedded System
a) Differentiate between application specific instruction set processor and general purpose processor. [4] b) List and briefly explain any four operational quality attributes and any four non operational quality attributes of an embedded system.
Q3[2 Marks]Hardware Design Issues
What are the benefits of using Custom Single Purpose Processor (CSPP) over General Purpose Processor (GPP)? Describe the design steps for designing a CSPP with a suitable example.
Q4[8 Marks]Designing Embedded System with Microcontroller
a) What are the two different configurations of seven segment display? List the important operational features of 8051 microcontroller. [2+2] b) Generate a square wave of 50% duty cycle in P 2.5 pin of 8051 microcontroller using assembly language programming. The crystal frequency is . Use timer 0, mode 1 to generate the time delay of .
Q5[6 Marks]RTOS Based Embedded System Design
a) Define deadlock. What are the Coffman’s conditions for deadlock? [2+4] b) Three processes with process IDs P1 ,P2, P3 with estimated completion time 10, 5, 7 ms and priorities 1, 3, 2 (0-highest priority, 3-lowest priority) respectively enters the ready queue together. A new process P4 with estimated completion time 6 ms and priority 0 enters the Ready queue after 5 ms of start of execution of P1. Calculate waiting time, turn around time, average waiting time and average turn around time in priority based preemptive scheduling. Assume all the processes contain only CPU operation and no I/O operations are involved.
Q6[8 Marks]VHDL Coding and Logic Synthesis
Draw a state diagram for a sequence detector for the sequence 1001 and then write a VHDL code based on the state diagram.
Q7[6 Marks]IC Technology
Explain the steps involved in manufacturing of an IC.

Curriculum Syllabus & Course Topics

Sourced from TU curriculum portal
Full Syllabus (PDF)Micro Syllabus (PDF)
Chapter-wise Units & Micro-Syllabus Topics (8 Units)

  1. 1. Introduction

    • 1.1Definition of embedded system
    • 1.2Embedded system vs. general purpose computing system
    • 1.3Characteristics, classification and purposes of embedded system
    • 1.4Major application areas of embedded systems

  2. 2. Core of Embedded System

    • 2.1Elements and core of embedded system
    • 2.1.1General purpose and domain specific processors: Microprocessor, microcontroller, digital signal processor (DSP)
    • 2.1.2Application specific integrated circuits (ASICS)
    • 2.1.3Programmable logic devices (PLDS)
    • 2.1.4Commercial off-the-shelf components (COTS)
    • 2.2Sensors and actuators: LED, 7 segment display, optocoupler, stepper motor, relay, Piezo buzzer, push button switch, keyboard, PPI
    • 2.3Communication interface: I2C, SPI bus, UART, 1 – wire interface, parallel interface, IEEE 1394 (Firewire), Wi-Fi, Zigbee, Bluetooth
    • 2.4Embedded firmware, real- time clock (RTC) and watchdog timer
    • 2.5Quality attributes of embedded systems
    • 2.5.1Operational quality attributes: Response, throughput, reliability, maintainability, security and safety
    • 2.5.2Non-operational quality attributes: Testability and debug-ability, evolvability, portability, time to prototype and market and per unit cost and NRE cost

  3. 3. Hardware Design Issues

    • 3.1Transistors and logic gates: Logic gates implementation using CMOS
    • 3.2Review of combinational logic
    • 3.3Review of sequential logic
    • 3.4Design of custom single/dual purpose processor design
    • 3.5Optimization of custom single/dual purpose processor design

  4. 4. Designing Embedded System with Microcontroller

    • 4.1Microprocessor versus microcontroller
    • 4.2Factors for selecting a microcontroller (Overview of 8051/AVR/PIC/ARM cortex microcontroller)
    • 4.3Pin description of 8051
    • 4.4Designing with 8051
    • 4.4.18051 architecture
    • 4.4.2Memory organization: Program and data memory, external program and data memory interfacing
    • 4.4.3Registers
    • 4.4.4Interrupt and interrupt systems
    • 4.5Timer units
    • 4.6Addressing modes and instruction set of 8051
    • 4.7Assembly programming

  5. 5. Embedded System Development Environment

    • 5.1Integrated development environment (IDE)
    • 5.2Keil µVision 3/4 IDE for 8051
    • 5.3An overview of ides for embedded system development
    • 5.4Files generated on cross – compilation: List file (.lst), preprocessor output file, object file (.obj), map file (.map), hex file (.hex)
    • 5.5Simulators, emulators and debugging

  6. 6. RTOS Based Embedded System Design

    • 6.1OS basics
    • 6.1.1Definition and primary functions
    • 6.1.2Kernel and its services: Process management, primary and secondary storage management, file system management, I/O devices management, protection, interrupt handler
    • 6.1.3Kernel space and user space: Monolithic and micro kernels
    • 6.2Types of OS: General purpose and real time OS
    • 6.3RT kernel and its basics functions
    • 6.3.1Task / process management
    • 6.3.2Task / process scheduling
    • 6.3.3Task / process synchronization
    • 6.3.4Error / exception handling
    • 6.3.5Memory management
    • 6.3.6Interrupt handling
    • 6.3.7Time management
    • 6.4Hard real time and soft real time
    • 6.5Process: Structure of process, process state and transition and PCB
    • 6.6Threads
    • 6.6.1Concept of multithreading
    • 6.6.2Thread standards: POSIX threads, Win32 threads, java threads
    • 6.6.3Thread preemption: User level thread, kernel/system level thread, many-to-one model, one-to-one model, many-to-many model
    • 6.6.4Thread vs. process
    • 6.7Multiprocessing and multitasking: preemptive, non – preemptive and cooperative
    • 6.8Task scheduling
    • 6.8.1Factors for selecting a scheduling criterion
    • 6.8.2Non-preemptive scheduling: FCFS/FIFO, LCFS/LIFO, SJF, priority based
    • 6.8.3Preemptive scheduling: SRTF, RR, priority based
    • 6.9Deadlock
    • 6.9.1Conditions for deadlock
    • 6.9.2Deadlock handling: Ignore deadlocks, detect and recover, avoid deadlocks, prevent deadlocks, livelock and starvation
    • 6.10How to choose an RTOS
    • 6.10.1Functional requirements
    • 6.10.2Non – functional requirements

  7. 7. VHDL Coding and Logic Synthesis

    • 7.1Introduction, features, application, design flow and code structure
    • 7.2VHDL modeling styles: Behavioral model, dataflow model and structural model
    • 7.3Lexical elements: Library and packages, identifiers, keywords, numbers, character, string, data objects, data types, operator, data type conversion
    • 7.4Dataflow model: Concurrent statements
    • 7.5Behavioral modeling: Sequential statements
    • 7.6Structural modeling
    • 7.7Finite state machine (FSM) design using VHDL: Coding of counter, register, sequence detector and custom single/dual purpose processor

  8. 8. IC Technology

    • 8.1Introduction
    • 8.2Full-custom (VLSI) IC technology
    • 8.3Semi-custom (ASIC) IC technology
    • 8.4Programmable logic devices (PLD) IC technology

Examination Scheme & Marks Distribution

Evaluation Structure

  • Final Board Theory Exam: 60 Marks (Pass mark: 24)
  • Internal Assessment: 40 Marks (Pass mark: 16)
  • Practical / Lab Exam: 25 or 50 Marks (Continuous lab evaluation + viva, where applicable)

* This is the general current IOE 60/40 scheme; verify course-specific details in the syllabus above.

Exam Preparation Guidelines

  • Review the available past examination paper to understand question styling, typical derivation topics, and marks allocation.
  • Cross-reference key answers with official syllabus units, standard textbooks, and lecture notes.
  • Structure answers with labeled diagrams, concise bullet points, and highlight final answers in numerical solutions.
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