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ENEX 302Bachelor in Electronics, Communication and Information Engineering · Semester 51 Paper Available

Embedded Systems

Past examination question papers and complete curriculum syllabus for Embedded Systems (ENEX 302), Bachelor in Electronics, Communication and Information Engineering Semester 5 under Institute of Engineering (IOE), Tribhuvan University.

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Most Frequently Asked Questions

Top recurring IOE board exam questions for Embedded Systems with verified mark schemes, formula notation, and recurrence frequency.

Showing 30 of 30 top repeated questions

Introduction

6 Questions
#1Repeated 3 Times[6 Marks]Introduction
Compare RISC and CISC architectures in embedded processors. Explain Harvard vs Princeton (Von Neumann) memory architecture and their performance impact on pipelining.
Appeared in:2082 Chaitra2080 Ashwin2078 Kartik
#2Repeated 3 Times[6 Marks]Introduction
Explain Memory Hierarchy and Cache Memory in high-performance embedded systems. Discuss cache mapping techniques (Direct Mapped, Fully Associative, Set-Associative) and cache write policies (Write-Through vs Write-Back).
Appeared in:2082 Chaitra2079 Chaitra2077 Magh
#3Repeated 2 Times[5 Marks]Introduction
Define embedded system with its key characteristics. Differentiate between a simulator and an emulator in embedded system development.
Appeared in:2082 Chaitra2080 Ashwin
#4Repeated 2 Times[8 Marks]Introduction
Differentiate between Application Specific Instruction Set Processor (ASIP) and General Purpose Processor (GPP). List and explain four operational quality attributes and four non-operational quality attributes of an embedded system.
Appeared in:2082 Chaitra2079 Chaitra
#5Repeated 2 Times[5 Marks]Introduction
Explain the role and operation of a Watchdog Timer (WDT) in embedded systems. How does it facilitate self-recovery from software hang-ups and infinite loops?
Appeared in:2082 Chaitra2079 Chaitra
#6Repeated 2 Times[6 Marks]Introduction
Compare Harvard architecture with Von Neumann architecture in embedded processors. Explain the trade-offs between RISC and CISC architectures for low-power embedded designs.
Appeared in:2082 Chaitra2078 Chaitra

Hardware Design Issues

9 Questions
#1Repeated 3 Times[8 Marks]Hardware Design Issues
Explain the Controller Area Network (CAN) bus protocol. Describe CAN message frame format, bit stuffing, non-destructive bitwise arbitration using dominant and recessive bits, and error handling mechanisms in automotive applications.
Appeared in:2082 Chaitra2081 Chaitra2079 Chaitra
#2Repeated 3 Times[8 Marks]Hardware Design Issues
Explain Serial Peripheral Interface (SPI) and Inter-Integrated Circuit ($I^2C$) bus protocols. Compare them with respect to clock synchronization, transmission speed, multi-master arbitration, and pin count.
Appeared in:2082 Chaitra2080 Ashwin2078 Bhadra
#3Repeated 3 Times[6 Marks]Hardware Design Issues
Explain analog-to-digital converter (ADC) interfacing with microcontrollers. Compare Successive Approximation Register (SAR) ADC and Flash ADC in terms of conversion time, resolution, and hardware complexity.
Appeared in:2082 Chaitra2080 Ashwin2077 Magh
#4Repeated 3 Times[8 Marks]Hardware Design Issues
Explain Custom Single-Purpose Processor (FSMD) design for an embedded computing module. Design the datapath and control unit (Finite State Machine with Data) to compute the Greatest Common Divisor (GCD) of two 8-bit numbers using Euclid's subtraction algorithm.
Appeared in:2082 Chaitra2080 Ashwin2079 Chaitra
#5Repeated 3 Times[6 Marks]Hardware Design Issues
Describe Direct Memory Access (DMA) controller operation in embedded systems. Explain Burst mode, Cycle Stealing mode, and Transparent mode of DMA transfer.
Appeared in:2082 Chaitra2080 Ashwin2078 Bhadra
#6Repeated 2 Times[8 Marks]Hardware Design Issues
What are the benefits of using Custom Single Purpose Processor (CSPP) over General Purpose Processor (GPP)? Describe the step-by-step design procedure for designing a CSPP with a suitable example (FSMD, datapath and controller).
Appeared in:2082 Chaitra2078 Chaitra
#7Repeated 2 Times[8 Marks]Hardware Design Issues
Draw a state diagram for a sequence detector detecting the sequence 1001 and write the complete VHDL / Verilog hardware description code based on the state machine.
Appeared in:2082 Chaitra2079 Chaitra
#8Repeated 2 Times[8 Marks]Hardware Design Issues
Explain serial communication protocols used in embedded systems: compare I2C, SPI, and CAN in terms of bus topology, transfer speed, arbitration, and data framing.
Appeared in:2082 Chaitra2080 Chaitra
#9Repeated 2 Times[6 Marks]Hardware Design Issues
Explain the interfacing of a $16 \times 2$ LCD display and seven-segment display (common anode vs common cathode) with 8051 microcontroller with circuit diagrams and initialization sequences.
Appeared in:2082 Chaitra2078 Chaitra

Designing Embedded System with Microcontroller

4 Questions
#1Repeated 3 Times[8 Marks]Designing Embedded System with Microcontroller
Describe the architecture of ARM Cortex-M microcontrollers. Explain the NVIC (Nested Vectored Interrupt Controller), operational modes (Thread and Handler), and low-power sleep modes.
Appeared in:2082 Chaitra2081 Chaitra2079 Chaitra
#2Repeated 3 Times[6 Marks]Designing Embedded System with Microcontroller
What is a Watchdog Timer (WDT) in embedded systems? How does it safeguard system reliability in critical automotive and industrial controllers against infinite loops or software hangs?
Appeared in:2082 Chaitra2081 Chaitra2078 Bhadra
#3Repeated 2 Times[8 Marks]Designing Embedded System with Microcontroller
Draw the architectural block diagram of the 8051 microcontroller. Explain special function registers (SFRs), memory organization, and internal timer/counter operational modes.
Appeared in:2082 Chaitra2080 Chaitra
#4Repeated 2 Times[8 Marks]Designing Embedded System with Microcontroller
Generate a square wave of $50\%$ duty cycle on pin P2.5 of 8051 microcontroller using assembly language programming. Given crystal frequency $11.0592\text{ MHz}$, use Timer 0 in Mode 1 to generate a precise time delay of $120\text{ ms}$.
Appeared in:2082 Chaitra2079 Chaitra

RTOS Based Embedded System Design

7 Questions
#1Repeated 4 Times[8 Marks]RTOS Based Embedded System Design
Explain Priority Inversion in real-time embedded systems. Describe how Priority Inheritance Protocol (PIP) and Priority Ceiling Protocol (PCP) prevent unbounded priority inversion with an illustrative timing diagram.
Appeared in:2082 Chaitra2081 Chaitra2079 Chaitra2077 Magh
#2Repeated 3 Times[8 Marks]RTOS Based Embedded System Design
Explain Real-Time Task Scheduling algorithms: Rate Monotonic Scheduling (RMS) and Earliest Deadline First (EDF). State their utilization bounds $U = N(2^{1/N} - 1)$ and $U \le 1$, and determine schedulability of a given periodic task set.
Appeared in:2082 Chaitra2080 Ashwin2078 Kartik
#3Repeated 3 Times[8 Marks]RTOS Based Embedded System Design
Explain Inter-Process Communication (IPC) and Synchronization mechanisms in RTOS: Binary Semaphores, Counting Semaphores, Mutexes with ownership, and Message Queues. Explain conditions leading to Deadlock and Coffman's conditions.
Appeared in:2082 Chaitra2081 Chaitra2079 Chaitra
#4Repeated 2 Times[6 Marks]RTOS Based Embedded System Design
Define deadlock. What are Coffman's four conditions for deadlock to occur in an embedded system? Explain deadlock prevention and avoidance mechanisms.
Appeared in:2082 Chaitra2081 Chaitra
#5Repeated 2 Times[6 Marks]RTOS Based Embedded System Design
Given processes with arrival times, estimated completion times, and priorities, compute waiting time, turnaround time, average waiting time, and average turnaround time using preemptive priority-based scheduling.
Appeared in:2082 Chaitra2081 Chaitra
#6Repeated 2 Times[8 Marks]RTOS Based Embedded System Design
Explain real-time task scheduling algorithms: Rate Monotonic Scheduling (RMS) and Earliest Deadline First (EDF). Evaluate the schedulability bound $\sum \frac{C_i}{T_i} \le n(2^{1/n}-1)$ and draw execution Gantt charts.
Appeared in:2082 Chaitra2080 Chaitra
#7Repeated 2 Times[7 Marks]RTOS Based Embedded System Design
What is Priority Inversion in real-time embedded systems? Explain the Mars Pathfinder incident and describe how Priority Inheritance Protocol (PIP) and Priority Ceiling Protocol (PCP) resolve it.
Appeared in:2082 Chaitra2079 Chaitra

IC Technology

4 Questions
#1Repeated 3 Times[8 Marks]IC Technology
Compare Full-Custom ASIC, Semi-Custom ASIC (Standard Cell and Gate Array), and Field Programmable Gate Array (FPGA) design methodologies in terms of Non-Recurring Engineering (NRE) cost, unit cost, performance, and time-to-market.
Appeared in:2082 Chaitra2081 Chaitra2078 Kartik
#2Repeated 3 Times[6 Marks]IC Technology
What is Low-Power Embedded Design? Explain dynamic power dissipation $P_{dyn} = \alpha C V_{dd}^2 f$ and static leakage current. Discuss Dynamic Voltage and Frequency Scaling (DVFS) and power gating techniques.
Appeared in:2082 Chaitra2080 Ashwin2078 Kartik
#3Repeated 2 Times[6 Marks]IC Technology
Explain the steps involved in the manufacturing of an Integrated Circuit (IC) / VLSI chip: wafer preparation, oxidation, photolithography, etching, ion implantation, metallization, and packaging.
Appeared in:2082 Chaitra2078 Chaitra
#4Repeated 2 Times[6 Marks]IC Technology
Compare Field Programmable Gate Arrays (FPGA) with Application-Specific Integrated Circuits (ASIC) with respect to NRE cost, design flexibility, performance, and volume production.
Appeared in:2082 Chaitra2080 Chaitra

Curriculum Syllabus & Course Topics

Sourced from TU curriculum portal
Full Syllabus (PDF)Micro Syllabus (PDF)
Chapter-wise Units & Micro-Syllabus Topics (8 Units)

  1. 1. Introduction

    • 1.1Definition of embedded system
    • 1.2Embedded system vs. general purpose computing system
    • 1.3Characteristics, classification and purposes of embedded system
    • 1.4Major application areas of embedded systems

  2. 2. Core of Embedded System

    • 2.1Elements and core of embedded system
    • 2.1.1General purpose and domain specific processors: Microprocessor, microcontroller, digital signal processor (DSP)
    • 2.1.2Application specific integrated circuits (ASICS)
    • 2.1.3Programmable logic devices (PLDS)
    • 2.1.4Commercial off-the-shelf components (COTS)
    • 2.2Sensors and actuators: LED, 7 segment display, optocoupler, stepper motor, relay, Piezo buzzer, push button switch, keyboard, PPI
    • 2.3Communication interface: I2C, SPI bus, UART, 1 – wire interface, parallel interface, IEEE 1394 (Firewire), Wi-Fi, Zigbee, Bluetooth
    • 2.4Embedded firmware, real- time clock (RTC) and watchdog timer
    • 2.5Quality attributes of embedded systems
    • 2.5.1Operational quality attributes: Response, throughput, reliability, maintainability, security and safety
    • 2.5.2Non-operational quality attributes: Testability and debug-ability, evolvability, portability, time to prototype and market and per unit cost and NRE cost

  3. 3. Hardware Design Issues

    • 3.1Transistors and logic gates: Logic gates implementation using CMOS
    • 3.2Review of combinational logic
    • 3.3Review of sequential logic
    • 3.4Design of custom single/dual purpose processor design
    • 3.5Optimization of custom single/dual purpose processor design

  4. 4. Designing Embedded System with Microcontroller

    • 4.1Microprocessor versus microcontroller
    • 4.2Factors for selecting a microcontroller (Overview of 8051/AVR/PIC/ARM cortex microcontroller)
    • 4.3Pin description of 8051
    • 4.4Designing with 8051
    • 4.4.18051 architecture
    • 4.4.2Memory organization: Program and data memory, external program and data memory interfacing
    • 4.4.3Registers
    • 4.4.4Interrupt and interrupt systems
    • 4.5Timer units
    • 4.6Addressing modes and instruction set of 8051
    • 4.7Assembly programming

  5. 5. Embedded System Development Environment

    • 5.1Integrated development environment (IDE)
    • 5.2Keil µVision 3/4 IDE for 8051
    • 5.3An overview of ides for embedded system development
    • 5.4Files generated on cross – compilation: List file (.lst), preprocessor output file, object file (.obj), map file (.map), hex file (.hex)
    • 5.5Simulators, emulators and debugging

  6. 6. RTOS Based Embedded System Design

    • 6.1OS basics
    • 6.1.1Definition and primary functions
    • 6.1.2Kernel and its services: Process management, primary and secondary storage management, file system management, I/O devices management, protection, interrupt handler
    • 6.1.3Kernel space and user space: Monolithic and micro kernels
    • 6.2Types of OS: General purpose and real time OS
    • 6.3RT kernel and its basics functions
    • 6.3.1Task / process management
    • 6.3.2Task / process scheduling
    • 6.3.3Task / process synchronization
    • 6.3.4Error / exception handling
    • 6.3.5Memory management
    • 6.3.6Interrupt handling
    • 6.3.7Time management
    • 6.4Hard real time and soft real time
    • 6.5Process: Structure of process, process state and transition and PCB
    • 6.6Threads
    • 6.6.1Concept of multithreading
    • 6.6.2Thread standards: POSIX threads, Win32 threads, java threads
    • 6.6.3Thread preemption: User level thread, kernel/system level thread, many-to-one model, one-to-one model, many-to-many model
    • 6.6.4Thread vs. process
    • 6.7Multiprocessing and multitasking: preemptive, non – preemptive and cooperative
    • 6.8Task scheduling
    • 6.8.1Factors for selecting a scheduling criterion
    • 6.8.2Non-preemptive scheduling: FCFS/FIFO, LCFS/LIFO, SJF, priority based
    • 6.8.3Preemptive scheduling: SRTF, RR, priority based
    • 6.9Deadlock
    • 6.9.1Conditions for deadlock
    • 6.9.2Deadlock handling: Ignore deadlocks, detect and recover, avoid deadlocks, prevent deadlocks, livelock and starvation
    • 6.10How to choose an RTOS
    • 6.10.1Functional requirements
    • 6.10.2Non – functional requirements

  7. 7. VHDL Coding and Logic Synthesis

    • 7.1Introduction, features, application, design flow and code structure
    • 7.2VHDL modeling styles: Behavioral model, dataflow model and structural model
    • 7.3Lexical elements: Library and packages, identifiers, keywords, numbers, character, string, data objects, data types, operator, data type conversion
    • 7.4Dataflow model: Concurrent statements
    • 7.5Behavioral modeling: Sequential statements
    • 7.6Structural modeling
    • 7.7Finite state machine (FSM) design using VHDL: Coding of counter, register, sequence detector and custom single/dual purpose processor

  8. 8. IC Technology

    • 8.1Introduction
    • 8.2Full-custom (VLSI) IC technology
    • 8.3Semi-custom (ASIC) IC technology
    • 8.4Programmable logic devices (PLD) IC technology

Examination Scheme & Marks Distribution

Evaluation Structure

  • Final Board Theory Exam: 60 Marks (Pass mark: 24)
  • Internal Assessment: 40 Marks (Pass mark: 16)
  • Practical / Lab Exam: 25 or 50 Marks (Continuous lab evaluation + viva, where applicable)

* This is the general current IOE 60/40 scheme; verify course-specific details in the syllabus above.

Exam Preparation Guidelines

  • Review the available past examination paper to understand question styling, typical derivation topics, and marks allocation.
  • Cross-reference key answers with official syllabus units, standard textbooks, and lecture notes.
  • Structure answers with labeled diagrams, concise bullet points, and highlight final answers in numerical solutions.

Frequently Asked Questions (Embedded Systems)

Q: How can I download Embedded Systems past question papers?

You can preview or download the Embedded Systems question papers (PDF) directly using the built-in viewer on this page with zero redirects or paywalls.

Q: What is the pass mark for Embedded Systems?

The general current scheme is a 60-mark final theory exam and a 40-mark internal assessment, with pass marks of 24 and 16. Verify the course-specific syllabus above.

Q: Where can I find the complete syllabus for this subject?

The available chapter-wise syllabus and topic breakdown is indexed in the Syllabus section above, with links to the curriculum PDF source.

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