#1Repeated 5 Times[8 Marks]Introduction
Define addressing modes. Explain the different types of addressing modes with suitable examples and compare each of them.
Appeared in:2082 Bhadra2081 Bhadra2080 Bhadra2075 Chaitra2074 Chaitra
ENEX 253Bachelor in Electronics, Communication and Information Engineering · Semester 42 Papers Available
Computer Organization and Architecture
Past examination question papers and complete curriculum syllabus for Computer Organization and Architecture (ENEX 253), Bachelor in Electronics, Communication and Information Engineering Semester 4 under Institute of Engineering (IOE), Tribhuvan University.
Past Question Papers (PDF)
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Most Frequently Asked Questions
Top recurring IOE board exam questions for Computer Organization and Architecture with verified mark schemes, formula notation, and recurrence frequency.
Showing 30 of 30 top repeated questions
Introduction
5 Questions#2Repeated 4 Times[8 Marks]Introduction
Write down the code to evaluate the arithmetic statement $Y = (A - B / C) \times [D + (E \times G)]$ using zero-address, one-address, two-address, and three-address instructions.
Appeared in:2081 Baishakh2080 Bhadra2075 Ashwin2073 Shrawan
#3Repeated 3 Times[8 Marks]Introduction
Design a 2-bit ALU that can perform subtraction, AND, OR, and XOR operations with function table and logic diagram.
Appeared in:2075 Chaitra2071 Chaitra2067 Ashadh
#4Repeated 2 Times[6 Marks]Introduction
Compare RISC and CISC architectures with respect to instruction set complexity, register usage, memory operands, pipelining, and clock cycle per instruction (CPI).
Appeared in:2082 Kartik2081 Chaitra
#5Repeated 2 Times[8 Marks]Introduction
Explain the Instruction Cycle: Fetch, Decode, Read Effective Address, Execute, and Interrupt. Draw the flowchart of the complete instruction cycle.
Appeared in:2082 Kartik2080 Chaitra
Control Unit (CU)
2 Questions#1Repeated 5 Times[8 Marks]Control Unit (CU)
Differentiate between hardwired control unit and microprogrammed control unit. Draw and explain the block diagram of microprogrammed control organization and address sequencing.
Appeared in:2082 Bhadra2080 Bhadra2075 Chaitra2073 Shrawan2071 Chaitra
#2Repeated 2 Times[8 Marks]Control Unit (CU)
Explain Microprogrammed Control Unit organization. Describe horizontal versus vertical microinstructions, address sequencing, and microinstruction formatting.
Appeared in:2082 Kartik2081 Chaitra
Memory System
5 Questions#1Repeated 5 Times[8 Marks]Memory System
Explain various mapping methods used in cache memory organization (Direct mapping, Associative mapping, and Set-associative mapping) and compare each with suitable diagrams.
Appeared in:2082 Bhadra2081 Bhadra2080 Bhadra2075 Chaitra2073 Shrawan
#2Repeated 4 Times[8 Marks]Memory System
Explain Least Recently Used (LRU) replacement algorithm in case of hit and miss. Suppose main memory has 64 blocks and cache has 16 lines; determine the size of tag, line, and word fields.
Appeared in:2082 Bhadra2075 Chaitra2075 Ashwin2068 Baishakh
#3Repeated 2 Times[6 Marks]Memory System
Explain the memory hierarchy in modern computer systems. What is Locality of Reference (Temporal and Spatial)? How does it justify the use of cache memory?
Appeared in:2082 Kartik2081 Chaitra
#4Repeated 2 Times[8 Marks]Memory System
Explain cache memory mapping techniques: Direct Mapping, Fully Associative Mapping, and Set-Associative Mapping. A system has a $64\text{ KB}$ cache with 16-byte blocks and a $16\text{ MB}$ main memory. Find Tag, Set/Index, and Word bits for 4-way set-associative mapping.
Appeared in:2082 Kartik2080 Chaitra
#5Repeated 2 Times[6 Marks]Memory System
Explain cache write policies: Write-Through vs Write-Back, and Write-Allocate vs No-Write-Allocate. Explain cache replacement algorithms (LRU, FIFO, Random).
Appeared in:2081 Chaitra2079 Chaitra
Computer Arithmetic
5 Questions#1Repeated 5 Times[8 Marks]Computer Arithmetic
Draw the flowchart of Booth's multiplication algorithm and multiply $(-7) \times (-10)$ using Booth's algorithm.
Appeared in:2081 Bhadra2075 Chaitra2074 Chaitra2073 Shrawan2071 Chaitra
#2Repeated 4 Times[8 Marks]Computer Arithmetic
Describe the procedure for floating-point addition and subtraction with the help of a detailed flowchart.
Appeared in:2081 Bhadra2075 Ashwin2071 Chaitra2068 Chaitra
#3Repeated 4 Times[8 Marks]Computer Arithmetic
Differentiate between restoring division and non-restoring division algorithms. Perform the division of $10 / 3$ using restoring division algorithm.
Appeared in:2080 Bhadra2075 Chaitra2073 Shrawan2070 Ashad
#4Repeated 2 Times[8 Marks]Computer Arithmetic
Explain Restoring and Non-Restoring division algorithms for unsigned binary integers. Trace Non-Restoring division for dividing dividend $11$ by divisor $3$ using 4-bit registers.
Appeared in:2082 Kartik2081 Chaitra
#5Repeated 2 Times[6 Marks]Computer Arithmetic
Explain IEEE 754 standard for single-precision (32-bit) and double-precision (64-bit) floating-point representation. Represent $-12.625_{10}$ in IEEE 754 single-precision format.
Appeared in:2081 Chaitra2079 Chaitra
Pipelining and Vector Processing
4 Questions#1Repeated 5 Times[8 Marks]Pipelining and Vector Processing
How pipeline processing is done in an instruction pipeline? Explain four-segment instruction pipeline with timing diagram. What are the major pipeline hazards and how are they resolved?
Appeared in:2081 Bhadra2080 Bhadra2075 Ashwin2074 Chaitra2071 Chaitra
#2Repeated 2 Times[8 Marks]Pipelining and Vector Processing
Explain instruction pipelining and calculate pipeline speedup, throughput, and efficiency. A 4-segment instruction pipeline has stage delays of $20\text{ ns}, 30\text{ ns}, 15\text{ ns}, 25\text{ ns}$. Calculate speedup over non-pipelined execution for 100 instructions.
Appeared in:2082 Kartik2080 Chaitra
#3Repeated 2 Times[8 Marks]Pipelining and Vector Processing
Explain pipeline hazards: Structural Hazards, Data Hazards (RAW, WAR, WAW), and Control (Branch) Hazards. How are data hazards resolved using operand forwarding and delayed branching?
Appeared in:2081 Chaitra2079 Baishakh
#4Repeated 2 Times[6 Marks]Pipelining and Vector Processing
Explain Flynn's classification of computer architectures (SISD, SIMD, MISD, MIMD) with examples and architectural diagrams.
Appeared in:2082 Shrawan2078 Bhadra
Input/ Output
5 Questions#1Repeated 4 Times[8 Marks]Input/ Output
Compare Programmed I/O, Interrupt-driven I/O, and Direct Memory Access (DMA). How does a DMA controller transfer data between high-speed peripheral and memory?
Appeared in:2075 Chaitra2075 Ashwin2071 Chaitra2070 Ashad
#2Repeated 4 Times[8 Marks]Input/ Output
Why is an Input-Output Processor (IOP) needed in an input-output organization? Explain how CPU and IOP communicate with each other.
Appeared in:2074 Chaitra2073 Shrawan2071 Chaitra2068 Chaitra
#3Repeated 3 Times[6 Marks]Input/ Output
Differentiate between isolated I/O and memory-mapped I/O. Explain with block diagram and control signal requirements.
Appeared in:2082 Bhadra2078 Bhadra2068 Baishakh
#4Repeated 2 Times[8 Marks]Input/ Output
Explain Programmed I/O, Interrupt-Driven I/O, and Direct Memory Access (DMA). Compare their CPU overheads and data transfer bandwidths.
Appeared in:2082 Kartik2081 Chaitra
#5Repeated 2 Times[6 Marks]Input/ Output
Explain daisy-chaining and priority encoder mechanisms for resolving simultaneous bus requests from multiple I/O devices.
Appeared in:2081 Chaitra2078 Bhadra
Multiprocessor System
4 Questions#1Repeated 4 Times[6 Marks]Multiprocessor System
Differentiate between tightly coupled multiprocessor and loosely coupled multiprocessor systems with neat block diagrams.
Appeared in:2081 Bhadra2080 Bhadra2076 Chaitra2074 Chaitra
#2Repeated 4 Times[8 Marks]Multiprocessor System
Compare and contrast the interconnection structures used in multiprocessor systems: Time-shared common bus, Multiport memory, Crossbar switch, and Hypercube network.
Appeared in:2082 Bhadra2080 Bhadra2074 Chaitra2068 Baishakh
#3Repeated 3 Times[6 Marks]Multiprocessor System
Explain inter-processor synchronization with suitable example. What is mutual exclusion with a semaphore and how is it implemented?
Appeared in:2075 Chaitra2074 Chaitra2071 Chaitra
#4Repeated 2 Times[8 Marks]Multiprocessor System
Explain cache coherence problem in shared-memory multiprocessor systems. Explain Snooping protocol (MESI protocol) and Directory-based protocol for maintaining cache coherence.
Appeared in:2082 Kartik2080 Baishakh
Curriculum Syllabus & Course Topics
Sourced from TU curriculum portalChapter-wise Units & Micro-Syllabus Topics (8 Units)
1. Introduction
- 1.1Organization and Architecture
- 1.2Structure of a computer, single processor, multi-core computer
- 1.3Performance Assessment 1.3.1 Clock speed and instruction per second 1.3.2 Instruction execution rate: CPI, MIPS rate, MFLOPS rate, arithmetic mean, harmonic mean, speed metric, geometric mean, rate metric, Amdahl’s law, speed up
- 1.4Computer function Instruction Fetch and Execute Instruction cycle state diagram Numerical examples on performance assessment
- 1.5Computer component, interconnection structure, bus interconnection, PCI
- 1.6RISC architecture, Overlapped register window Berkeley RISC
2. Central Processing Unit (CPU)
- 2.1Processor Bus Organization
- 2.2Processor register Organization: Control word, examples of microoperations
- 2.3Stack Organization Register stack, memory stack, reverse polish notation, evaluation of arithmetic expressions
- 2.4Instruction formats: CPU organization, zero and more address instruction formats
- 2.5Addressing modes: Types, examples, strengths and weaknesses
- 2.6Instruction set
- 2.7Status bit conditions
- 2.8Interrupt: Definition, types, processing and ISR
3. Control Unit (CU)
- 3.1Hardwired control unit
- 3.2Microprogrammed control unit
- 3.3Microinstructions, control memory organization, Wilkes control
- 3.4Microinstruction sequencing: Design considerations, sequencing techniques, address generation, microinstruction encoding
- 3.5Application of microprogramming
- 3.6Microinstruction execution
4. Memory System
- 4.1Characteristics of memory system
- 4.2Memory classification and hierarchy
- 4.3Semiconductor memory and its types, read only memory, read/write memory
- 4.4RAM modules and interfaces: DDR, DIMM and SODIMM
- 4.5Cache memory
- 4.6External Memory
5. Computer Arithmetic
- 5.1ALU (Arithmetic and logic unit)
- 5.2Integer representation: Sign-magnitude representation, two’s complement representation, converting between different bit lengths, fixed-point representation
- 5.3Integer arithmetic
- 5.4Floating-point arithmetic
6. Pipelining and Vector Processing
- 6.1Pipelining and its importance
- 6.2Instruction and arithmetic pipelining
- 6.3Pipelining hazards: Data, structural and control hazards
- 6.4RISC pipeline
- 6.5Parallel processing
- 6.6Vector processing
- 6.7Array processors: Attached array processor and SIMD array processor
7. Input/ Output
- 7.1External devices
- 7.2I/O modules: Module function, module structure
- 7.3Programmed I/O, I/O commands, I/O instructions, flowchart
- 7.4Interrupt driven I/O, interrupt processing and flowchart
- 7.5Direct memory access (DMA): Drawbacks of programmed and interrupt driven I/O, DMA function, typical DMA block diagram and possible DMA configuration
- 7.6I/O channels and processors: The evolution of the I/O function, characteristics of I/O channels
- 7.7The external interface: Types of interfaces, point- to point and multiple configurations, small computer system interface (SCSI)
8. Multiprocessor System
- 8.1Multiprocessor computers and their characteristics
- 8.2Multi-core computers and their architecture
- 8.3Interconnection structure: Time-shared common bus, multiport memory, crossbar switch, multistage switching network and hypercube system
- 8.4Interprocessor arbitration
- 8.5Interprocessor communication and Synchronization
Examination Scheme & Marks Distribution
Evaluation Structure
- Final Board Theory Exam: 60 Marks (Pass mark: 24)
- Internal Assessment: 40 Marks (Pass mark: 16)
- Practical / Lab Exam: 25 or 50 Marks (Continuous lab evaluation + viva, where applicable)
* This is the general current IOE 60/40 scheme; verify course-specific details in the syllabus above.
Exam Preparation Guidelines
- Review the 2 available past examination papers to identify recurring patterns, core problem types, and chapter weightage.
- Cross-reference key answers with official syllabus units, standard textbooks, and lecture notes.
- Structure answers with labeled diagrams, concise bullet points, and highlight final answers in numerical solutions.
Frequently Asked Questions (Computer Organization and Architecture)
Q: How can I download Computer Organization and Architecture past question papers?
You can preview or download the Computer Organization and Architecture question papers (PDF) directly using the built-in viewer on this page with zero redirects or paywalls.
Q: What is the pass mark for Computer Organization and Architecture?
The general current scheme is a 60-mark final theory exam and a 40-mark internal assessment, with pass marks of 24 and 16. Verify the course-specific syllabus above.
Q: Where can I find the complete syllabus for this subject?
The available chapter-wise syllabus and topic breakdown is indexed in the Syllabus section above, with links to the curriculum PDF source.
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Curriculum Syllabus & Marking Scheme