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ENEX 202Bachelor in Electronics, Communication and Information Engineering Ā· Semester 31 Paper Available

Advanced Electronics

Past examination question papers and complete curriculum syllabus for Advanced Electronics (ENEX 202), Bachelor in Electronics, Communication and Information Engineering Semester 3 under Institute of Engineering (IOE), Tribhuvan University.

Past Question Papers (PDF)

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Note: This question paper file (4th sem) was archived from an IOE exam session for the common Advanced Electronics curriculum.

4th-sem_Advanced Electronics.pdf

IOE Past Examination Paper

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Most Frequently Asked Questions

Top recurring IOE board exam questions for Advanced Electronics with verified mark schemes, formula notation, and recurrence frequency.

Showing 30 of 30 top repeated questions

Operational Amplifier Characterization

4 Questions
#1Repeated 5 Times[8 Marks]Operational Amplifier Characterization
Define slew rate of an operational amplifier. An op-amp has a slew rate of $0.5\text{ V}/\mu\text{s}$ and closed-loop gain of $33$. The input signal is given by $v_{in} = 0.01\sin(10^6 t) + 0.05\sin(350 \times 10^3 t)$ (or $0.1\sin(200000 t)$). Determine whether the output is distorted due to slew rate limitation. If so, suggest a remedy.
Appeared in:2082 Kartik2081 Chaitra2080 Chaitra2078 Chaitra2077 Chaitra
#2Repeated 4 Times[8 Marks]Operational Amplifier Characterization
Why is the output current of a simple current mirror circuit not exactly equal to reference current? Derive an expression for the current gain and output resistance of a Widlar current source with necessary circuit diagrams.
Appeared in:2082 Kartik2081 Chaitra2080 Chaitra2078 Chaitra
#3Repeated 3 Times[8 Marks]Operational Amplifier Characterization
Define input bias current and input offset current of an op-amp. What is their effect on the output voltage? How can the effect of input bias current be reduced or compensated in an op-amp circuit?
Appeared in:2081 Chaitra2080 Chaitra2078 Chaitra
#4Repeated 2 Times[7 Marks]Operational Amplifier Characterization
Show that the voltage gain of a differential amplifier with active load is twice that of a differential amplifier with passive load.
Appeared in:2077 Chaitra2075 Chaitra

Digital-to-Analog and Analog-to-Digital Conversion

7 Questions
#1Repeated 5 Times[8 Marks]Digital-to-Analog and Analog-to-Digital Conversion
What are the advantages of an R-2R ladder DAC over a binary-weighted resistor DAC? Derive the expression for the output voltage of an inverted R-2R ladder DAC and show that the output voltage ranges from $0$ to $-V_{\text{ref}}$.
Appeared in:2082 Kartik2081 Chaitra2080 Chaitra2078 Chaitra2077 Chaitra
#2Repeated 3 Times[8 Marks]Digital-to-Analog and Analog-to-Digital Conversion
Explain R-2R Ladder Digital-to-Analog Converter (DAC) in voltage and current modes. Derive the output voltage $V_o = -V_{ref} \sum_{i=1}^n \frac{b_i}{2^i}$. Why is the R-2R ladder preferred over binary weighted-resistor DACs for high resolution (12-16 bits)?
Appeared in:2082 Kartik2080 Chaitra2077 Magh
#3Repeated 3 Times[8 Marks]Digital-to-Analog and Analog-to-Digital Conversion
Explain Dual-Slope Integrating Analog-to-Digital Converter (ADC). Derive the relation showing conversion result $N = \frac{V_{in}}{V_{ref}} 2^n$ is independent of integrator $R, C$ values and clock frequency drift. Why is it used in digital multimeters?
Appeared in:2082 Kartik2081 Chaitra2078 Chaitra
#4Repeated 3 Times[8 Marks]Digital-to-Analog and Analog-to-Digital Conversion
Explain Successive Approximation Register (SAR) ADC. Detail the binary search conversion sequence with D/A converter, sample-and-hold circuit, and comparator. Calculate conversion time for an 8-bit SAR ADC clocked at $2\text{ MHz}$.
Appeared in:2082 Kartik2080 Chaitra2076 Chaitra
#5Repeated 3 Times[8 Marks]Digital-to-Analog and Analog-to-Digital Conversion
Describe Sigma-Delta ($\Sigma\Delta$) ADC architecture: Over-sampling ($f_s \gg 2 f_B$), 1-bit DAC/ADC, Noise Shaping with loop integrator, and Digital Decimation Filter. Why do Sigma-Delta ADCs achieve ultra-high 24-bit resolution at audio frequencies?
Appeared in:2082 Kartik2081 Chaitra2079 Chaitra
#6Repeated 2 Times[8 Marks]Digital-to-Analog and Analog-to-Digital Conversion
Explain the working of a Successive Approximation Register (SAR) ADC in brief with a suitable example for a 6-bit ADC with $V_{\text{ref}} = 16\text{ V}$ and $V_{in} = 10.25\text{ V}$.
Appeared in:2081 Chaitra2079 Chaitra
#7Repeated 2 Times[8 Marks]Digital-to-Analog and Analog-to-Digital Conversion
Explain the operation of a Dual-Slope Integrating ADC with circuit diagram, timing waveforms, and mathematical derivation. An 8-bit dual slope ADC has $R = 20\text{ k}\Omega$ and $C = 0.001\ \mu\text{F}$. An analog input of $-0.25\text{ V}$ is integrated for $T_1 = 150\ \mu\text{s}$. (a) What is the maximum integrator voltage reached? (b) If switched to $+5\text{ V}$ reference, how long does it take to reach $0\text{ V}$? (c) If clock is $3.125\text{ MHz}$, what is the digital output?
Appeared in:2080 Chaitra2078 Chaitra

Instrumentation and Isolation Amplifiers

4 Questions
#1Repeated 4 Times[8 Marks]Instrumentation and Isolation Amplifiers
List out characteristics and application areas of an Instrumentation Amplifier. Derive the expression for the differential voltage gain of a three-op-amp instrumentation amplifier.
Appeared in:2082 Kartik2081 Chaitra2080 Chaitra2077 Chaitra
#2Repeated 3 Times[6 Marks]Instrumentation and Isolation Amplifiers
List out applications of isolation amplifiers. Explain the operation of an optically coupled isolation amplifier and a transformer-coupled isolation amplifier.
Appeared in:2081 Chaitra2080 Chaitra2077 Chaitra
#3Repeated 3 Times[8 Marks]Instrumentation and Isolation Amplifiers
Derive the voltage gain $A_v = \left(1 + \frac{2 R_1}{R_g}\right)\left(\frac{R_3}{R_2}\right)$ and Common-Mode Rejection Ratio (CMRR) of a three-op-amp Instrumentation Amplifier. Why does it provide exceptionally high input impedance and high CMRR without matched source impedances?
Appeared in:2082 Kartik2081 Chaitra2078 Chaitra
#4Repeated 3 Times[8 Marks]Instrumentation and Isolation Amplifiers
Explain Isolation Amplifiers. Compare Transformer-Coupled, Optically-Coupled, and Capacitively-Coupled isolation amplifiers with respect to barrier breakdown voltage, common-mode rejection, and medical bio-potential isolation applications.
Appeared in:2082 Kartik2080 Chaitra2077 Chaitra

Operational Amplifier-Bipolar Transistor Logarithmic Amplifier

2 Questions
#1Repeated 3 Times[7 Marks]Operational Amplifier-Bipolar Transistor Logarithmic Amplifier
What are the advantages of a transistor logarithmic amplifier over a diode logarithmic amplifier? Derive the output voltage expression of a logarithmic amplifier using a matched transistor pair.
Appeared in:2081 Chaitra2078 Chaitra2077 Chaitra
#2Repeated 3 Times[8 Marks]Operational Amplifier-Bipolar Transistor Logarithmic Amplifier
Derive the output voltage of a Translog (BJT-based) Logarithmic Amplifier: $v_o = -V_T \ln\left(\frac{v_i}{I_s R}\right)$. Explain why uncompensated log amplifiers suffer severe temperature drift due to $V_T$ and $I_s$, and describe the dual-transistor temperature compensation circuit.
Appeared in:2082 Kartik2081 Chaitra2079 Chaitra

Log-Antilog Circuit Application

4 Questions
#1Repeated 3 Times[8 Marks]Log-Antilog Circuit Application
Design an Analog Multiplier and Divider circuit using Log and Anti-log amplifiers and summing op-amps based on the mathematical identity $\ln(v_1 v_2) = \ln v_1 + \ln v_2$ and $\ln(v_1 / v_2) = \ln v_1 - \ln v_2$.
Appeared in:2082 Kartik2080 Chaitra2076 Chaitra
#2Repeated 3 Times[8 Marks]Log-Antilog Circuit Application
Explain the Analog Four-Quadrant Gilbert Multiplier Cell. Derive the differential output current as a function of the hyperbolic tangent of differential input voltages: $I_{out} = I_0 \tanh\left(\frac{v_1}{2V_T}\right)\tanh\left(\frac{v_2}{2V_T}\right)$.
Appeared in:2082 Kartik2081 Chaitra2078 Bhadra
#3Repeated 2 Times[7 Marks]Log-Antilog Circuit Application
Implement the mathematical expression $V_o = V_1^2 + V_2^2 - V_1 \sqrt{V_2}$ (or $V_o = V_1^2 - V_2^2 + V_1 V_2$) using log, antilog, summer, and subtractor op-amp circuits.
Appeared in:2081 Chaitra2080 Chaitra
#4Repeated 2 Times[7 Marks]Log-Antilog Circuit Application
Draw the detailed circuit diagram of a four-quadrant analog multiplier and derive its input-output relationship using log and antilog circuits.
Appeared in:2078 Chaitra2077 Chaitra

Power Electronics

4 Questions
#1Repeated 3 Times[8 Marks]Power Electronics
Explain the working principle and two-transistor analogy (model) of a Silicon Controlled Rectifier (SCR). Sketch its V-I characteristics curve and discuss its turn-on and turn-off mechanisms.
Appeared in:2081 Chaitra2080 Chaitra2077 Chaitra
#2Repeated 3 Times[8 Marks]Power Electronics
Explain the operation of a step-down (Buck) chopper for RLE load with the help of mathematical equations and waveforms. Show that maximum ripple current is present when duty cycle $k = 0.5$.
Appeared in:2082 Kartik2081 Chaitra2080 Chaitra
#3Repeated 3 Times[8 Marks]Power Electronics
Explain the Silicon Controlled Rectifier (SCR / Thyristor): Two-transistor analogy (p-n-p and n-p-n regenerative feedback), turn-on mechanisms, latching vs holding currents, and turn-off commutation techniques (Natural vs Forced commutation).
Appeared in:2082 Kartik2081 Chaitra2079 Chaitra
#4Repeated 2 Times[8 Marks]Power Electronics
Define chopper and inverter. Explain the working of a single-phase full-bridge inverter with necessary circuit diagrams and waveforms.
Appeared in:2081 Chaitra2080 Chaitra

Switched Mode Power Supplies and Drives

5 Questions
#1Repeated 3 Times[8 Marks]Switched Mode Power Supplies and Drives
A Buck-Boost regulator has an input voltage $V_s = 12\text{ V}$, duty cycle $k = 0.25$, and switching frequency $f = 25\text{ kHz}$. Inductance $L = 150\ \mu\text{H}$ and filter capacitance $C = 220\ \mu\text{F}$. Determine: (a) The average output voltage $V_a$, (b) The peak-to-peak output ripple voltage $\Delta V_c$, (c) The peak-to-peak ripple current of inductor $\Delta I$, and (d) The critical values of $L$ and $C$.
Appeared in:2082 Kartik2080 Chaitra2077 Chaitra
#2Repeated 3 Times[8 Marks]Switched Mode Power Supplies and Drives
Explain the Buck (Step-Down) DC-DC Converter. Derive the continuous conduction mode (CCM) voltage conversion ratio $V_o / V_s = D$, inductor current ripple $\Delta I_L$, and the minimum critical inductance $L_{min}$ to avoid discontinuous conduction.
Appeared in:2082 Kartik2080 Chaitra2077 Chaitra
#3Repeated 3 Times[8 Marks]Switched Mode Power Supplies and Drives
Explain Boost (Step-Up) and Buck-Boost DC-DC Converters. Derive their output voltage conversion ratios $V_o / V_s = \frac{1}{1 - D}$ and $V_o / V_s = -\frac{D}{1 - D}$, sketch inductor current waveforms, and calculate capacitor voltage ripple.
Appeared in:2082 Kartik2081 Chaitra2078 Bhadra
#4Repeated 3 Times[8 Marks]Switched Mode Power Supplies and Drives
Explain Isolated SMPS Topologies: Flyback Converter and Forward Converter. Contrast transformer core demagnetization (tertiary reset winding), transformer utilization, and peak transistor stress in offline power supplies.
Appeared in:2082 Kartik2080 Chaitra2076 Chaitra
#5Repeated 3 Times[8 Marks]Switched Mode Power Supplies and Drives
Explain H-Bridge DC Motor Drives using power MOSFETs/IGBTs. Describe Bipolar and Unipolar Pulse Width Modulation (PWM) switching schemes, shoot-through prevention using dead-time control, and freewheeling diode protection.
Appeared in:2082 Kartik2080 Chaitra2077 Magh

Curriculum Syllabus & Course Topics

Sourced from TU curriculum portal
Full Syllabus (PDF)
Chapter-wise Units & Micro-Syllabus Topics (7 Units)

  1. 1. Operational Amplifier Characterization

    • 1.1Input offset voltage
    • 1.2Input bias and input offset currents
    • 1.3Output impedance
    • 1.4Differential and common-mode input impedance
    • 1.5DC gain, bandwidth, gain-bandwidth product
    • 1.6Common-mode and power supply rejection ratio
    • 1.7Higher frequency poles settling time
    • 1.8Slew rate
    • 1.9Noise in operational amplifier circuits

  2. 2. Digital-to-Analog and Analog-to-Digital Conversion

    • 2.1Performance parameters of DAC and ADC
    • 2.2Binary weighted resistor DAC
    • 2.3The R-2R ladder DAC
    • 2.4Unipolar and bipolar D/A converters
    • 2.5Count-up and tracking A/Dā€™s based on D/Aā€™s
    • 2.6Successive approximation A/D converters
    • 2.7Integrating voltage-to-time conversion A/D converters, dual and quad slope types
    • 2.8Sigma delta A/D converters
    • 2.9Flash A/D converters

  3. 3. Instrumentation and Isolation Amplifiers

    • 3.1One and two operational amplifier instrumentation amplifiers
    • 3.2The three operational amplifier instrumentation amplifier
    • 3.3Consideration of non-ideal properties
    • 3.4Isolation amplifier principles and realization
    • 3.5Consideration of non-ideal properties

  4. 4. Operational Amplifier-Bipolar Transistor Logarithmic Amplifier

    • 4.1The basic logarithmic amplifier
    • 4.2Non-ideal effects
    • 4.3Stability consideration
    • 4.4Anti-logarithmic operations

  5. 5. Log-Antilog Circuit Application

    • 5.1Analog multiplier based on log-antilog principles
    • 5.2The multifunction converter circuit
    • 5.3Proportional to absolute temperature (PTAT) devices
    • 5.4RMS to DC conversion

  6. 6. Power Electronics

    • 6.1Power diodes, power MOSFET V-I characteristics
    • 6.2Thyristor: V-I, turn on-off mechanism, protection schemes, firing circuits, series/parallel combination, self and forced commutation
    • 6.3Members of thyristor family: DIAC, TRIAC
    • 6.4Controlled rectifier circuits: single phase half wave and full wave with RLE load
    • 6.5Inverters: Fixed voltage variable frequency (half and full), variable voltage variable frequency (PWM inverters)
    • 6.6Choppers: Principle of operation, control strategies, step up chopper, classification of chopper circuits

  7. 7. Switched Mode Power Supplies and Drives

    • 7.1Switch mode power supply
    • 7.2Buck, boost, buck-boost regulator
    • 7.3DC drives: classification and choice of selection
    • 7.4Review of characteristics and operating modes of DC motors
    • 7.5Half wave and full wave single phase converters drives
    • 7.6Stepper motor and drives

Examination Scheme & Marks Distribution

Evaluation Structure

  • Final Board Theory Exam: 60 Marks (Pass mark: 24)
  • Internal Assessment: 40 Marks (Pass mark: 16)
  • Practical / Lab Exam: 25 or 50 Marks (Continuous lab evaluation + viva, where applicable)

* This is the general current IOE 60/40 scheme; verify course-specific details in the syllabus above.

Exam Preparation Guidelines

  • Review the available past examination paper to understand question styling, typical derivation topics, and marks allocation.
  • Practice drawing labeled circuit schematics, deriving transfer functions, and showing systematic mathematical steps.
  • Structure answers with labeled diagrams, concise bullet points, and highlight final answers in numerical solutions.

Frequently Asked Questions (Advanced Electronics)

Q: How can I download Advanced Electronics past question papers?

You can preview or download the Advanced Electronics question papers (PDF) directly using the built-in viewer on this page with zero redirects or paywalls.

Q: What is the pass mark for Advanced Electronics?

The general current scheme is a 60-mark final theory exam and a 40-mark internal assessment, with pass marks of 24 and 16. Verify the course-specific syllabus above.

Q: Where can I find the complete syllabus for this subject?

The available chapter-wise syllabus and topic breakdown is indexed in the Syllabus section above, with links to the curriculum PDF source.

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