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ENEX 201Bachelor in Electrical Engineering · Semester 32 Papers Available

Digital Logic

Past examination question papers and complete curriculum syllabus for Digital Logic (ENEX 201), Bachelor in Electrical Engineering Semester 3 under Institute of Engineering (IOE), Tribhuvan University.

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3rd-sem_Digital Logic.pdf

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Most Frequently Asked Questions

Top recurring IOE board exam questions for Digital Logic with verified mark schemes, formula notation, and recurrence frequency.

Showing 30 of 30 top repeated questions

Introduction

2 Questions
#1Repeated 2 Times[6 Marks]Introduction
Differentiate between positive logic and negative logic with truth table examples. Perform binary subtraction using 1's complement and 2's complement arithmetic: $(11010)_2 - (10111)_2$.
Appeared in:2082 Baishakh2081 Bhadra
#2Repeated 2 Times[6 Marks]Introduction
Differentiate between analog signal and digital signal. Explain error detecting and correcting codes. Generate a 7-bit even parity Hamming code for the 4-bit data word $1011$.
Appeared in:2082 Shrawan2079 Baishakh

Logic Gates

3 Questions
#1Repeated 5 Times[4 Marks]Logic Gates
State and explain De Morgan's Theorem with truth table and necessary diagrams.
Appeared in:2082 Bhadra2080 Bhadra2079 Bhadra2078 Bhadra2076 Chaitra
#2Repeated 4 Times[3 Marks]Logic Gates
Show that NAND and NOR gates are universal gates.
Appeared in:2083 Baishakh2080 Bhadra2078 Bhadra2058 Baishakh
#3Repeated 2 Times[6 Marks]Logic Gates
Why are NAND and NOR gates called universal gates? Realize basic gates (AND, OR, NOT) and XOR gate using only two-input NOR gates.
Appeared in:2081 Bhadra2080 Bhadra

Boolean Algebra and K-Maps

4 Questions
#1Asked in 7 Exam Sessions[8 Marks]Boolean Algebra and K-Maps
Minimize the function $F(A, B, C, D) = \sum m(0, 1, 2, 8, 9, 10, 11, 14, 15)$ using the Quine-McCluskey (Tabular) method. Find all prime implicants and essential prime implicants using the prime implicant selection table.
Appeared in:2081 Chaitra2079 Chaitra2076 Baisakh2074 Chaitra2072 Chaitra2069 Chaitra2066 Chaitra
#2Repeated 5 Times[5 Marks]Boolean Algebra and K-Maps
Minimize the function $F(A, B, C, D) = \sum m(0, 1, 2, 4, 7, 8, 9, 10, 12, 15) + d(5, 11, 13)$ using K-Map and realize it with suitable logic gates.
Appeared in:2082 Bhadra2080 Bhadra2078 Bhadra2075 Ashwin2074 Ashwin
#3Repeated 4 Times[5 Marks]Boolean Algebra and K-Maps
Minimize the function $F(A, B, C, D) = \sum m(1, 2, 4, 5, 6, 8, 10, 11, 13, 15)$ using K-Map and realize it with suitable logic gates.
Appeared in:2083 Baishakh2081 Baishakh2079 Bhadra2076 Chaitra
#4Repeated 2 Times[8 Marks]Boolean Algebra and K-Maps
Simplify the Boolean function using Quine-McCluskey (Tabulation) method: $F(A, B, C, D) = \sum m(0, 1, 2, 8, 10, 11, 14, 15) + d(9, 13)$. List all prime implicants and essential prime implicants.
Appeared in:2082 Shrawan2081 Bhadra

Combinational Logic Circuits

7 Questions
#1Repeated 4 Times[4 Marks]Combinational Logic Circuits
Implement a full subtractor circuit using multiplexer.
Appeared in:2083 Baishakh2082 Shrawan2079 Bhadra2076 Ashwin
#2Repeated 4 Times[6 Marks]Combinational Logic Circuits
What is magnitude comparator? Design a 3-bit magnitude comparator.
Appeared in:2082 Bhadra2080 Baishakh2078 Kartik2075 Chaitra
#3Repeated 4 Times[8 Marks]Combinational Logic Circuits
What is a decoder? Design an octal priority encoder with neat circuit diagram.
Appeared in:2082 Baishakh2079 Bhadra2075 Ashwin2074 Ashwin
#4Repeated 3 Times[4 Marks]Combinational Logic Circuits
Design the simplest logic circuit for 'f' segment for the BCD-to-seven segment display decoder.
Appeared in:2081 Ashwin2078 Bhadra2075 Chaitra
#5Repeated 2 Times[8 Marks]Combinational Logic Circuits
Design a 4-bit Carry Look-Ahead Adder (CLA). Explain how it eliminates the ripple carry delay inherent in a Parallel Binary Adder.
Appeared in:2082 Baishakh2080 Baishakh
#6Repeated 2 Times[8 Marks]Combinational Logic Circuits
Realize a Full Subtractor circuit using a single $3 \times 8$ active-low Decoder and external NAND gates. Draw the logic diagram and truth table.
Appeared in:2082 Baishakh2081 Bhadra
#7Repeated 2 Times[8 Marks]Combinational Logic Circuits
Implement the Boolean function $F(A, B, C, D) = \sum m(1, 3, 4, 11, 12, 13, 14, 15)$ using an $8:1$ Multiplexer with A, B, C as select lines.
Appeared in:2082 Shrawan2079 Bhadra

Sequential Logic Circuits

4 Questions
#1Repeated 5 Times[7 Marks]Sequential Logic Circuits
Differentiate between combinational circuit and sequential circuit. With necessary steps and implementation, Convert SR flip flop into JK flip flop.
Appeared in:2082 Bhadra2081 Baishakh2080 Bhadra2080 Baishakh2078 Bhadra
#2Repeated 4 Times[7 Marks]Sequential Logic Circuits
Differentiate between latch and flipflop. Modify a D flip-flop such that it functions as a JK flip-flop.
Appeared in:2083 Baishakh2081 Baishakh2079 Bhadra2076 Chaitra
#3Repeated 2 Times[8 Marks]Sequential Logic Circuits
What is the race-around condition in a JK flip-flop? Explain how it is eliminated in a Master-Slave JK Flip-Flop with a circuit diagram and timing waveforms.
Appeared in:2082 Baishakh2081 Bhadra
#4Repeated 2 Times[6 Marks]Sequential Logic Circuits
Show the conversion of a JK flip-flop to a D flip-flop and a T flip-flop. Derive the excitation tables and minimal combinational logic.
Appeared in:2082 Shrawan2078 Bhadra

Registers and Counters

6 Questions
#1Repeated 4 Times[5 Marks]Registers and Counters
Write briefly about different types of shift registers. With necessary circuit and timing diagrams, explain the operation of how the shift register is used as a Johnson's Counter.
Appeared in:2082 Bhadra2080 Baishakh2078 Kartik2075 Chaitra
#2Repeated 4 Times[5 Marks]Registers and Counters
Describe the operation of asynchronous BCD (decade) counter with necessary diagrams.
Appeared in:2083 Baishakh2078 Bhadra2075 Ashwin2072 Chaitra
#3Repeated 4 Times[7 Marks]Registers and Counters
Design the synchronous mod-10 up counter using T flip-flop and draw its timing diagram also.
Appeared in:2083 Baishakh2080 Baishakh2078 Kartik2074 Chaitra
#4Repeated 2 Times[8 Marks]Registers and Counters
Design a synchronous 3-bit Up/Down counter using JK flip-flops with an external mode control input $M$ ($M=0$ for Up count, $M=1$ for Down count).
Appeared in:2082 Baishakh2081 Bhadra
#5Repeated 2 Times[8 Marks]Registers and Counters
Design a 4-bit Universal Shift Register capable of Serial In Serial Out, Serial In Parallel Out, Parallel In Serial Out, and Parallel In Parallel Out operations using D flip-flops and 4:1 multiplexers.
Appeared in:2082 Shrawan2080 Bhadra
#6Repeated 2 Times[8 Marks]Registers and Counters
Design a Mod-12 Asynchronous (Ripple) counter using negative edge-triggered T flip-flops and draw the complete timing diagram.
Appeared in:2081 Bhadra2079 Baishakh

Sequential Machine Designs

2 Questions
#1Repeated 4 Times[7 Marks]Sequential Machine Designs
Design a synchronous sequential machine that has 1-bit serial input X and output Z which will be high when the input contains the message 110 (Use SR Flip Flop).
Appeared in:2082 Bhadra2081 Ashwin2079 Bhadra2076 Chaitra
#2Repeated 2 Times[10 Marks]Sequential Machine Designs
Design a synchronous sequential circuit (Mealy or Moore model) to detect an overlapping sequence '1011' from an incoming bit stream. Draw state diagram, state table, and circuit diagram using D flip-flops.
Appeared in:2082 Baishakh2081 Bhadra

Digital Integrated Circuits

2 Questions
#1Repeated 4 Times[6 Marks]Digital Integrated Circuits
Draw the circuit diagram of two-input CMOS NAND gate and explain its logic operation briefly and list the characteristics of TTL logic family.
Appeared in:2082 Baishakh2081 Ashwin2078 Bhadra2058 Baishakh
#2Repeated 2 Times[6 Marks]Digital Integrated Circuits
Define propagation delay, noise margin, fan-in, and fan-out of logic families. Compare TTL and CMOS logic families with respect to power dissipation, speed, and packaging density.
Appeared in:2082 Baishakh2080 Baishakh

Curriculum Syllabus & Course Topics

Sourced from TU curriculum portal
Full Syllabus (PDF)
Chapter-wise Units & Micro-Syllabus Topics (8 Units)

  1. 1. Introduction

    • 1.1Digital versus analog signals
    • 1.2Logic level diagram
    • 1.3Digital integrated circuits (ICs)
    • 1.4Clock triggering systems
    • 1.5Digital system applications
    • 1.6Digital codes and conversions
    • 1.6.1Decimal, binary, octal and hexadecimal codes
    • 1.6.2BCD code
    • 1.6.3Excess-3 code
    • 1.6.4Gray code
    • 1.6.5Examples of code conversions
    • 1.7Alphanumeric codes: ASCII code and EBCDIC code
    • 1.81’s complement and 2’s complement
    • 1.9Signed number representation

  2. 2. Logic Gates

    • 2.1Basic gates and their equivalents
    • 2.2Universal gates and their equivalents
    • 2.3Exclusive gates and their equivalents
    • 2.4Positive and negative logic
    • 2.5De’Morgan’s laws
    • 2.6Applications of logic gates

  3. 3. Boolean Algebra and K-Maps

    • 3.1Boolean algebra and its laws
    • 3.2Simplifications of Boolean expressions
    • 3.3Minterms and maxterms
    • 3.4Sum-of-product and product-of-sum methods
    • 3.5Truth tables and Karnaugh map
    • 3.6Four variables K-maps.
    • 3.7Cell, pairs, quads and octets
    • 3.8Rolling, envelop effects and redundant groups
    • 3.9Don’t care conditions

  4. 4. Combinational Logic Circuits

    • 4.1Design procedures
    • 4.2Half-adder and full-adder
    • 4.3Half-subtractor and full-subtractor
    • 4.4Ripple carry adders and fast adders
    • 4.5Multiplexers design
    • 4.6Demultiplexers design
    • 4.7Basic encoders
    • 4.8Priority encoders
    • 4.9Encoder designs
    • 4.10Decoder designs
    • 4.11BCD-to-decimal decoder
    • 4.12Seven-segment decoder
    • 4.13Magnitude comparators

  5. 5. Sequential Logic Circuits

    • 5.1Latches and flip-flops: SR, D, T and JK
    • 5.2Excitation tables, characteristic equations
    • 5.3Master-slave flip-flops
    • 5.4Flip-flop timing diagrams
    • 5.5Flip-flops as the state machines
    • 5.6Flip-flop conversions
    • 5.7Flip-flop applications

  6. 6. Registers and Counters

    • 6.1Register fundamentals, register types
    • 6.2SISO, SIPO, PISO and PIPO registers
    • 6.3Data transfer timing diagrams
    • 6.4Asynchronous counters
    • 6.5Up, down and mod-n asynchronous counters
    • 6.6Synchronous counters
    • 6.7Up, down and mod-n synchronous counters
    • 6.8Register and counter applications

  7. 7. Sequential Machine Designs

    • 7.1Machine design procedures
    • 7.2Primitive state diagrams
    • 7.3Transition/flow tables
    • 7.4Redundant states
    • 7.5Pure binary assignment tables
    • 7.6Excitation maps
    • 7.7Realization of the models
    • 7.8Circuit diagram of synchronous machine
    • 7.9One-bit and two-bit input sequence detectors

  8. 8. Digital Integrated Circuits

    • 8.1BJT and MOSFET switching circuits
    • 8.2TTL parameters
    • 8.3TTL circuits: NAND, NOT, NOR
    • 8.4CMOS parameters
    • 8.5CMOS logic circuits: NAND, NOR, NOT
    • 8.6Three-state TTL devices
    • 8.7Digital devices applications
    • 8.7.1Multiplexing displays
    • 8.7.2Frequency counters
    • 8.7.3Time measurements

Examination Scheme & Marks Distribution

Evaluation Structure

  • Final Board Theory Exam: 60 Marks (Pass mark: 24)
  • Internal Assessment: 40 Marks (Pass mark: 16)
  • Practical / Lab Exam: 25 or 50 Marks (Continuous lab evaluation + viva, where applicable)

* This is the general current IOE 60/40 scheme; verify course-specific details in the syllabus above.

Exam Preparation Guidelines

  • Review the 2 available past examination papers to identify recurring patterns, core problem types, and chapter weightage.
  • Cross-reference key answers with official syllabus units, standard textbooks, and lecture notes.
  • Structure answers with labeled diagrams, concise bullet points, and highlight final answers in numerical solutions.

Frequently Asked Questions (Digital Logic)

Q: How can I download Digital Logic past question papers?

You can preview or download the Digital Logic question papers (PDF) directly using the built-in viewer on this page with zero redirects or paywalls.

Q: What is the pass mark for Digital Logic?

The general current scheme is a 60-mark final theory exam and a 40-mark internal assessment, with pass marks of 24 and 16. Verify the course-specific syllabus above.

Q: Where can I find the complete syllabus for this subject?

The available chapter-wise syllabus and topic breakdown is indexed in the Syllabus section above, with links to the curriculum PDF source.

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