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ENEX 201Bachelor in Electrical Engineering · Semester 32 Papers Available

Digital Logic

Past examination question papers and complete curriculum syllabus for Digital Logic (ENEX 201), Bachelor in Electrical Engineering Semester 3 under Institute of Engineering (IOE), Tribhuvan University.

Sem 3 Subjects (5)View Full Semester Overview →
ENSH 201Engineering Mathematics IIIENEE 201Electric Circuit IIENEX 201Digital LogicENEE 202Electrical MachinesENCE 201Applied Dynamics
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Past Question Papers (PDF)

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3rd-sem_Digital Logic.pdf

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Most Frequently Asked Questions

Top recurring IOE board exam questions for Digital Logic with verified mark schemes, formula notation, and recurrence frequency.

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Year-wise & Session-wise Exam Papers

Complete questions from each exam session (Regular & Back exams from 2082 to 2069) for Digital Logic. Click any session paper to expand.

Showing 267 questions across 19 exam session papers
Institute of Engineering • 2083 Baishakh Board Examination
Q1[3 Marks]Boolean Algebra and K-Maps
Using Boolean algebra prove the following logic functions: Where, is the XOR function.
Q2[3 Marks]Combinational Logic Circuits
Realize a full-adder logic circuit using a single 4:1 multiplexer and necessary logic gates. Draw a 2-input TTL NOR gate logic circuit and define shortly its logic function with truth table.
Q3[2 Marks]Combinational Logic Circuits
What is a decoder? List the design procedures while designing a combinational logic circuit and apply those procedures in the design of decimal priority encoder.
Q4[6 Marks]Registers and Counters
Construct mod-14 asynchronous counter using T flip-flops with negative edge triggering clock.
Q5[6 Marks]Digital Integrated Circuits
Explain how the second section of the digital clock works, describe with necessary diagrams.
Q6[8 Marks]Introduction
Perform the following conversions as indicated: [3×1] (a) (b) (c)
Q7[5 Marks]Logic Gates
Realize a full-substractor logic circuit using a single 1:4 demultiplexer and necessary logic gates.
Q8[7 Marks]Introduction
Obtain the simplest logic function using K-map for the following logic function and draw its logic circuit.
Q9[7 Marks]Registers and Counters📐 Diagram in Paper
Explain a PISO shift register with negative edge triggering clock using D flip-flops and also draw its timing diagram when parallel input data of 1011 to serial data out.
Q10[7 Marks]Introduction
Design 3-bit Gray code synchronous up counter using JK flip-flop with positive edge clock.
Q11[2 Marks]Combinational Logic Circuits
What is a multiplexing display? How is it applied in the modern LED display system? Explain it with the example of the common-cathode type seven segment LED display system.
Q12[12 Marks]Sequential Machine Designs
Design a sequential machine that consists of a single input, X and the single output, Z. The machine is required to give output high when input contains serial message 1101 sequence. Use SR flip-flops only.

Curriculum Syllabus & Course Topics

Sourced from TU curriculum portal
Full Syllabus (PDF)
Chapter-wise Units & Micro-Syllabus Topics (8 Units)

  1. 1. Introduction

    • 1.1Digital versus analog signals
    • 1.2Logic level diagram
    • 1.3Digital integrated circuits (ICs)
    • 1.4Clock triggering systems
    • 1.5Digital system applications
    • 1.6Digital codes and conversions
    • 1.6.1Decimal, binary, octal and hexadecimal codes
    • 1.6.2BCD code
    • 1.6.3Excess-3 code
    • 1.6.4Gray code
    • 1.6.5Examples of code conversions
    • 1.7Alphanumeric codes: ASCII code and EBCDIC code
    • 1.81’s complement and 2’s complement
    • 1.9Signed number representation

  2. 2. Logic Gates

    • 2.1Basic gates and their equivalents
    • 2.2Universal gates and their equivalents
    • 2.3Exclusive gates and their equivalents
    • 2.4Positive and negative logic
    • 2.5De’Morgan’s laws
    • 2.6Applications of logic gates

  3. 3. Boolean Algebra and K-Maps

    • 3.1Boolean algebra and its laws
    • 3.2Simplifications of Boolean expressions
    • 3.3Minterms and maxterms
    • 3.4Sum-of-product and product-of-sum methods
    • 3.5Truth tables and Karnaugh map
    • 3.6Four variables K-maps.
    • 3.7Cell, pairs, quads and octets
    • 3.8Rolling, envelop effects and redundant groups
    • 3.9Don’t care conditions

  4. 4. Combinational Logic Circuits

    • 4.1Design procedures
    • 4.2Half-adder and full-adder
    • 4.3Half-subtractor and full-subtractor
    • 4.4Ripple carry adders and fast adders
    • 4.5Multiplexers design
    • 4.6Demultiplexers design
    • 4.7Basic encoders
    • 4.8Priority encoders
    • 4.9Encoder designs
    • 4.10Decoder designs
    • 4.11BCD-to-decimal decoder
    • 4.12Seven-segment decoder
    • 4.13Magnitude comparators

  5. 5. Sequential Logic Circuits

    • 5.1Latches and flip-flops: SR, D, T and JK
    • 5.2Excitation tables, characteristic equations
    • 5.3Master-slave flip-flops
    • 5.4Flip-flop timing diagrams
    • 5.5Flip-flops as the state machines
    • 5.6Flip-flop conversions
    • 5.7Flip-flop applications

  6. 6. Registers and Counters

    • 6.1Register fundamentals, register types
    • 6.2SISO, SIPO, PISO and PIPO registers
    • 6.3Data transfer timing diagrams
    • 6.4Asynchronous counters
    • 6.5Up, down and mod-n asynchronous counters
    • 6.6Synchronous counters
    • 6.7Up, down and mod-n synchronous counters
    • 6.8Register and counter applications

  7. 7. Sequential Machine Designs

    • 7.1Machine design procedures
    • 7.2Primitive state diagrams
    • 7.3Transition/flow tables
    • 7.4Redundant states
    • 7.5Pure binary assignment tables
    • 7.6Excitation maps
    • 7.7Realization of the models
    • 7.8Circuit diagram of synchronous machine
    • 7.9One-bit and two-bit input sequence detectors

  8. 8. Digital Integrated Circuits

    • 8.1BJT and MOSFET switching circuits
    • 8.2TTL parameters
    • 8.3TTL circuits: NAND, NOT, NOR
    • 8.4CMOS parameters
    • 8.5CMOS logic circuits: NAND, NOR, NOT
    • 8.6Three-state TTL devices
    • 8.7Digital devices applications
    • 8.7.1Multiplexing displays
    • 8.7.2Frequency counters
    • 8.7.3Time measurements

Examination Scheme & Marks Distribution

Evaluation Structure

  • Final Board Theory Exam: 60 Marks (Pass mark: 24)
  • Internal Assessment: 40 Marks (Pass mark: 16)
  • Practical / Lab Exam: 25 or 50 Marks (Continuous lab evaluation + viva, where applicable)

* This is the general current IOE 60/40 scheme; verify course-specific details in the syllabus above.

Exam Preparation Guidelines

  • Review the 2 available past examination papers to identify recurring patterns, core problem types, and chapter weightage.
  • Cross-reference key answers with official syllabus units, standard textbooks, and lecture notes.
  • Structure answers with labeled diagrams, concise bullet points, and highlight final answers in numerical solutions.
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Curriculum Syllabus & Marking Scheme