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ENCT 303Bachelor in Computer Engineering · Semester 52 Papers Available

Computer Organization and Architecture

Past examination question papers and complete curriculum syllabus for Computer Organization and Architecture (ENCT 303), Bachelor in Computer Engineering Semester 5 under Institute of Engineering (IOE), Tribhuvan University.

Sem 5 Subjects (6)View Full Semester Overview →
ENSH 304Probability and StatisticsENCT 301Database Management SystemENCT 302Web Application ProgrammingENCT 303Computer Organization and ArchitectureENCT 304Computer NetworksENCT 325-344Elective I
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Past Question Papers (PDF)

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5th-sem_Computer Organization and Architecture.pdf

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Most Frequently Asked Questions

Top recurring IOE board exam questions for Computer Organization and Architecture with verified mark schemes, formula notation, and recurrence frequency.

Showing 40 of 40 top repeated questions
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Year-wise & Session-wise Exam Papers

Complete questions from each exam session (Regular & Back exams from 2082 to 2069) for Computer Organization and Architecture. Click any session paper to expand.

Showing 331 questions across 24 exam session papers
Institute of Engineering • 2083 Baishakh Board Examination
Q1[4 Marks]Central Processing Unit (CPU)
Explain the function of CPU. Design a 4-bit ALU that can perform addition, \n**[OR]**\n and AND operations.
Q2[6 Marks]Introduction
Explain the bus interconnection scheme with diagram.
Q3[5 Marks]Central Processing Unit (CPU)
Mention the different types of addressing modes. Compare each of them with algorithm as well as advantages and disadvantages.
Q4[6 Marks]Control Unit (CU)
Explain the address sequencing with the help of block diagram. Mention the various fields in microinstruction format.
Q5[5 Marks]Pipelining and Vector Processing
Explain the arithmetic pipelining with example. Discuss the different types of pipeline hazards with example.
Q6[5 Marks]Pipelining and Vector Processing
Divide using restoring division algorithm.
Q7[4 Marks]Input/ Output
Explain the Booth's multiplication algorithm and multiply using Booth's multiplication algorithm.
Q8[2 Marks]Central Processing Unit (CPU)
Differentiate between direct mapping and set associative mapping. Explain the Least Recently Used (LRU) replacement algorithm with example.
Q9[4 Marks]Central Processing Unit (CPU)
Explain the CPU and IOP communication channel using diagram.
Q10[5 Marks]Computer Arithmetic
Differentiate between tightly coupled multiprocessor and loosely coupled multiprocessor.

Curriculum Syllabus & Course Topics

Sourced from TU curriculum portal
Full Syllabus (PDF)Micro Syllabus (PDF)
Chapter-wise Units & Micro-Syllabus Topics (8 Units)

  1. 1. Introduction

    • 1.1Organization and Architecture
    • 1.2Structure of a computer, single processor, multi-core computer
    • 1.3Performance Assessment 1.3.1 Clock speed and instruction per second 1.3.2 Instruction execution rate: CPI, MIPS rate, MFLOPS rate, arithmetic mean, harmonic mean, speed metric, geometric mean, rate metric, Amdahl’s law, speed up
    • 1.4Computer function Instruction Fetch and Execute Instruction cycle state diagram Numerical examples on performance assessment
    • 1.5Computer component, interconnection structure, bus interconnection, PCI
    • 1.6RISC architecture, Overlapped register window Berkeley RISC

  2. 2. Central Processing Unit (CPU)

    • 2.1Processor Bus Organization
    • 2.2Processor register Organization: Control word, examples of microoperations
    • 2.3Stack Organization Register stack, memory stack, reverse polish notation, evaluation of arithmetic expressions
    • 2.4Instruction formats: CPU organization, zero and more address instruction formats
    • 2.5Addressing modes: Types, examples, strengths and weaknesses
    • 2.6Instruction set
    • 2.7Status bit conditions
    • 2.8Interrupt: Definition, types, processing and ISR

  3. 3. Control Unit (CU)

    • 3.1Hardwired control unit
    • 3.2Microprogrammed control unit
    • 3.3Microinstructions, control memory organization, Wilkes control
    • 3.4Microinstruction sequencing: Design considerations, sequencing techniques, address generation, microinstruction encoding
    • 3.5Application of microprogramming
    • 3.6Microinstruction execution

  4. 4. Memory System

    • 4.1Characteristics of memory system
    • 4.2Memory classification and hierarchy
    • 4.3Semiconductor memory and its types, read only memory, read/write memory
    • 4.4RAM modules and interfaces: DDR, DIMM and SODIMM
    • 4.5Cache memory
    • 4.6External Memory

  5. 5. Computer Arithmetic

    • 5.1ALU (Arithmetic and logic unit)
    • 5.2Integer representation: Sign-magnitude representation, two’s complement representation, converting between different bit lengths, fixed-point representation
    • 5.3Integer arithmetic
    • 5.4Floating-point arithmetic

  6. 6. Pipelining and Vector Processing

    • 6.1Pipelining and its importance
    • 6.2Instruction and arithmetic pipelining
    • 6.3Pipelining hazards: Data, structural and control hazards
    • 6.4RISC pipeline
    • 6.5Parallel processing
    • 6.6Vector processing
    • 6.7Array processors: Attached array processor and SIMD array processor

  7. 7. Input/ Output

    • 7.1External devices
    • 7.2I/O modules: Module function, module structure
    • 7.3Programmed I/O, I/O commands, I/O instructions, flowchart
    • 7.4Interrupt driven I/O, interrupt processing and flowchart
    • 7.5Direct memory access (DMA): Drawbacks of programmed and interrupt driven I/O, DMA function, typical DMA block diagram and possible DMA configuration
    • 7.6I/O channels and processors: The evolution of the I/O function, characteristics of I/O channels
    • 7.7The external interface: Types of interfaces, point- to point and multiple configurations, small computer system interface (SCSI)

  8. 8. Multiprocessor System

    • 8.1Multiprocessor computers and their characteristics
    • 8.2Multi-core computers and their architecture
    • 8.3Interconnection structure: Time-shared common bus, multiport memory, crossbar switch, multistage switching network and hypercube system
    • 8.4Interprocessor arbitration
    • 8.5Interprocessor communication and Synchronization

Examination Scheme & Marks Distribution

Evaluation Structure

  • Final Board Theory Exam: 60 Marks (Pass mark: 24)
  • Internal Assessment: 40 Marks (Pass mark: 16)
  • Practical / Lab Exam: 25 or 50 Marks (Continuous lab evaluation + viva, where applicable)

* This is the general current IOE 60/40 scheme; verify course-specific details in the syllabus above.

Exam Preparation Guidelines

  • Review the 2 available past examination papers to identify recurring patterns, core problem types, and chapter weightage.
  • Cross-reference key answers with official syllabus units, standard textbooks, and lecture notes.
  • Structure answers with labeled diagrams, concise bullet points, and highlight final answers in numerical solutions.
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Curriculum Syllabus & Marking Scheme