Subject Archive1 Paper Available

Digital Logic(BEI)

Past examination question papers available in the PDF viewer below. Review past questions and syllabus units to prepare for your semester final exams.

Past Question Papers (PDF)

Switch tabs to view different exam papers

1st-sem_Digital Logic(BEI).pdf

IOE Past Examination Paper

Download PDF

Served via fast CDN. Read in full view or download for offline study.

Drive Mirror ↗Direct Download ↓

Document information: This past examination paper is identified as an IOE/TU academic document and was cataloged from a public Google Drive archive. This independent website did not create the examination paper and is not affiliated with TU or IOE.

Rights holders can request correction or removal by emailing subeshgaming@gmail.com with this page URL and supporting details.

Most Frequently Asked Questions

Top recurring IOE board exam questions for Digital Logic(BEI) with verified mark schemes, formula notation, and recurrence frequency.

Showing 30 of 30 top repeated questions

Introduction

2 Questions

#1Repeated 2 Times[6 Marks]Introduction

Differentiate between positive logic and negative logic with truth table examples. Perform binary subtraction using 1's complement and 2's complement arithmetic: $(11010)_2 - (10111)_2$.

Appeared in:2082 Baishakh2081 Bhadra

#2Repeated 2 Times[6 Marks]Introduction

Differentiate between analog signal and digital signal. Explain error detecting and correcting codes. Generate a 7-bit even parity Hamming code for the 4-bit data word $1011$.

Appeared in:2082 Shrawan2079 Baishakh

Logic Gates

3 Questions

#1Repeated 5 Times[4 Marks]Logic Gates

State and explain De Morgan's Theorem with truth table and necessary diagrams.

Appeared in:2082 Bhadra2080 Bhadra2079 Bhadra2078 Bhadra2076 Chaitra

#2Repeated 4 Times[3 Marks]Logic Gates

Show that NAND and NOR gates are universal gates.

Appeared in:2083 Baishakh2080 Bhadra2078 Bhadra2058 Baishakh

#3Repeated 2 Times[6 Marks]Logic Gates

Why are NAND and NOR gates called universal gates? Realize basic gates (AND, OR, NOT) and XOR gate using only two-input NOR gates.

Appeared in:2081 Bhadra2080 Bhadra

Boolean Algebra and K-Maps

4 Questions

#1Asked in 7 Exam Sessions[8 Marks]Boolean Algebra and K-Maps

Minimize the function $F(A, B, C, D) = \sum m(0, 1, 2, 8, 9, 10, 11, 14, 15)$ using the Quine-McCluskey (Tabular) method. Find all prime implicants and essential prime implicants using the prime implicant selection table.

Appeared in:2081 Chaitra2079 Chaitra2076 Baisakh2074 Chaitra2072 Chaitra2069 Chaitra2066 Chaitra

#2Repeated 5 Times[5 Marks]Boolean Algebra and K-Maps

Minimize the function $F(A, B, C, D) = \sum m(0, 1, 2, 4, 7, 8, 9, 10, 12, 15) + d(5, 11, 13)$ using K-Map and realize it with suitable logic gates.

Appeared in:2082 Bhadra2080 Bhadra2078 Bhadra2075 Ashwin2074 Ashwin

#3Repeated 4 Times[5 Marks]Boolean Algebra and K-Maps

Minimize the function $F(A, B, C, D) = \sum m(1, 2, 4, 5, 6, 8, 10, 11, 13, 15)$ using K-Map and realize it with suitable logic gates.

Appeared in:2083 Baishakh2081 Baishakh2079 Bhadra2076 Chaitra

#4Repeated 2 Times[8 Marks]Boolean Algebra and K-Maps

Simplify the Boolean function using Quine-McCluskey (Tabulation) method: $F(A, B, C, D) = \sum m(0, 1, 2, 8, 10, 11, 14, 15) + d(9, 13)$. List all prime implicants and essential prime implicants.

Appeared in:2082 Shrawan2081 Bhadra

Combinational Logic Circuits

7 Questions

#1Repeated 4 Times[4 Marks]Combinational Logic Circuits

Implement a full subtractor circuit using multiplexer.

Appeared in:2083 Baishakh2082 Shrawan2079 Bhadra2076 Ashwin

#2Repeated 4 Times[6 Marks]Combinational Logic Circuits

What is magnitude comparator? Design a 3-bit magnitude comparator.

Appeared in:2082 Bhadra2080 Baishakh2078 Kartik2075 Chaitra

#3Repeated 4 Times[8 Marks]Combinational Logic Circuits

What is a decoder? Design an octal priority encoder with neat circuit diagram.

Appeared in:2082 Baishakh2079 Bhadra2075 Ashwin2074 Ashwin

#4Repeated 3 Times[4 Marks]Combinational Logic Circuits

Design the simplest logic circuit for 'f' segment for the BCD-to-seven segment display decoder.

Appeared in:2081 Ashwin2078 Bhadra2075 Chaitra

#5Repeated 2 Times[8 Marks]Combinational Logic Circuits

Design a 4-bit Carry Look-Ahead Adder (CLA). Explain how it eliminates the ripple carry delay inherent in a Parallel Binary Adder.

Appeared in:2082 Baishakh2080 Baishakh

#6Repeated 2 Times[8 Marks]Combinational Logic Circuits

Realize a Full Subtractor circuit using a single $3 \times 8$ active-low Decoder and external NAND gates. Draw the logic diagram and truth table.

Appeared in:2082 Baishakh2081 Bhadra

#7Repeated 2 Times[8 Marks]Combinational Logic Circuits

Implement the Boolean function $F(A, B, C, D) = \sum m(1, 3, 4, 11, 12, 13, 14, 15)$ using an $8:1$ Multiplexer with A, B, C as select lines.

Appeared in:2082 Shrawan2079 Bhadra

Sequential Logic Circuits

4 Questions

#1Repeated 5 Times[7 Marks]Sequential Logic Circuits

Differentiate between combinational circuit and sequential circuit. With necessary steps and implementation, Convert SR flip flop into JK flip flop.

Appeared in:2082 Bhadra2081 Baishakh2080 Bhadra2080 Baishakh2078 Bhadra

#2Repeated 4 Times[7 Marks]Sequential Logic Circuits

Differentiate between latch and flipflop. Modify a D flip-flop such that it functions as a JK flip-flop.

Appeared in:2083 Baishakh2081 Baishakh2079 Bhadra2076 Chaitra

#3Repeated 2 Times[8 Marks]Sequential Logic Circuits

What is the race-around condition in a JK flip-flop? Explain how it is eliminated in a Master-Slave JK Flip-Flop with a circuit diagram and timing waveforms.

Appeared in:2082 Baishakh2081 Bhadra

#4Repeated 2 Times[6 Marks]Sequential Logic Circuits

Show the conversion of a JK flip-flop to a D flip-flop and a T flip-flop. Derive the excitation tables and minimal combinational logic.

Appeared in:2082 Shrawan2078 Bhadra

Registers and Counters

6 Questions

#1Repeated 4 Times[5 Marks]Registers and Counters

Write briefly about different types of shift registers. With necessary circuit and timing diagrams, explain the operation of how the shift register is used as a Johnson's Counter.

Appeared in:2082 Bhadra2080 Baishakh2078 Kartik2075 Chaitra

#2Repeated 4 Times[5 Marks]Registers and Counters

Describe the operation of asynchronous BCD (decade) counter with necessary diagrams.

Appeared in:2083 Baishakh2078 Bhadra2075 Ashwin2072 Chaitra

#3Repeated 4 Times[7 Marks]Registers and Counters

Design the synchronous mod-10 up counter using T flip-flop and draw its timing diagram also.

Appeared in:2083 Baishakh2080 Baishakh2078 Kartik2074 Chaitra

#4Repeated 2 Times[8 Marks]Registers and Counters

Design a synchronous 3-bit Up/Down counter using JK flip-flops with an external mode control input $M$ ($M=0$ for Up count, $M=1$ for Down count).

Appeared in:2082 Baishakh2081 Bhadra

#5Repeated 2 Times[8 Marks]Registers and Counters

Design a 4-bit Universal Shift Register capable of Serial In Serial Out, Serial In Parallel Out, Parallel In Serial Out, and Parallel In Parallel Out operations using D flip-flops and 4:1 multiplexers.

Appeared in:2082 Shrawan2080 Bhadra

#6Repeated 2 Times[8 Marks]Registers and Counters

Design a Mod-12 Asynchronous (Ripple) counter using negative edge-triggered T flip-flops and draw the complete timing diagram.

Appeared in:2081 Bhadra2079 Baishakh

Sequential Machine Designs

2 Questions

#1Repeated 4 Times[7 Marks]Sequential Machine Designs

Design a synchronous sequential machine that has 1-bit serial input X and output Z which will be high when the input contains the message 110 (Use SR Flip Flop).

Appeared in:2082 Bhadra2081 Ashwin2079 Bhadra2076 Chaitra

#2Repeated 2 Times[10 Marks]Sequential Machine Designs

Design a synchronous sequential circuit (Mealy or Moore model) to detect an overlapping sequence '1011' from an incoming bit stream. Draw state diagram, state table, and circuit diagram using D flip-flops.

Appeared in:2082 Baishakh2081 Bhadra

Digital Integrated Circuits

2 Questions

#1Repeated 4 Times[6 Marks]Digital Integrated Circuits

Draw the circuit diagram of two-input CMOS NAND gate and explain its logic operation briefly and list the characteristics of TTL logic family.

Appeared in:2082 Baishakh2081 Ashwin2078 Bhadra2058 Baishakh

#2Repeated 2 Times[6 Marks]Digital Integrated Circuits

Define propagation delay, noise margin, fan-in, and fan-out of logic families. Compare TTL and CMOS logic families with respect to power dissipation, speed, and packaging density.

Appeared in:2082 Baishakh2080 Baishakh